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512 Kbit / 1 Mbit / 2 Mbit Serial Flash
SST45VF512 / SST45VF010 / SST45VF020
Advance Information
FEATURES: * Single 2.7-3.6V Read and Write Operations * Serial Interface Architecture - SPI Compatible: Mode 0 and Mode 3 * Byte Serial Read with Single Command * Superior Reliability - Endurance: 100,000 Cycles (typical) - Greater than 100 years Data Retention * Low Power Consumption: - Active Current: 20 mA (typical) - Standby Current: 10 A (typical) * Sector or Chip-Erase Capability - Uniform 4 KByte sectors * Fast Erase and Byte-Program: - Chip-Erase Time: 70 ms (typical) - Sector-Erase Time: 18 ms (typical) - Byte-Program Time: 14 s (typical) * Automatic Write Timing - Internal VPP Generation * End-of-Write Detection - Software Status * 10 MHz Max Clock Frequency * Hardware Reset Pin (RESET#) - Resets the device to Standby Mode * CMOS I/O Compatibility * Hardware Data Protection - Protects and unprotects the device from Write operation * Packages Available - 8-Pin SOIC (4.9mm x 6mm)
1 2 3 4 5 6 7
PRODUCT DESCRIPTION The SST45VF512, SST45VF010 and SST45VF020 are manufactured with SST's proprietary, high performance CMOS SuperFlash technology. The Serial Flash is organized as 16 sectors of 4096 Bytes for SST45VF512, 32 sectors of 4096 Bytes for the SST45VF010 and 64 sectors of 4096 Bytes for the SST45VF020. The memory is accessed for Read or Erase/Program by the SPI bus compatible serial protocol. The bus signals are: serial data input (SI), serial data output (SO), serial clock (SCK), write protect (WP#), chip enable (CE#), and hardware reset (RESET#). The SST45VFxxx devices are offered in 8-pin SOIC package. See Figure 1 for the pinout. Device Operation The SST45VFxxx uses bus cycles of 8 bits each for commands, data, and addresses to execute operations. The operation instructions are listed in Table 2. All instructions are synchronized off a high to low transition of CE#. The first low to high transition on SCK will initiate the instruction sequence. Inputs will be accepted on the rising edge of SCK starting with the most significant bit. Any low to high transition on CE# before the input instruction completes will terminate any instruction in progress and return the device to the standby mode.
Read The Read operation outputs the data in order from the initial accessed address. While SCK is input, the address will be incremented automatically until end (top) of the address space, then the internal address pointer automatically increments to beginning (bottom) of the address space (00000H), and data out stream will continue. The read data stream is continuous through all addresses until terminated by a low to high transition on CE#. Sector/Chip-Erase Operation The Sector-Erase operation clears all bits in the selected sector to "FF". The Chip-Erase instruction clears all bits in the device to "FF". Byte-Program Operation The Byte-Program operation programs the bits in the selected byte to the desired data. The selected byte must be in the erased state ("FF") when initiating a Program operation. The data is input from bit 7 to bit 0 in order. Software Status Operation The Status operation determines if an Erase or Program operation is in progress. If bit 0 is at a "0" an Erase or Program operation is in progress, the device is busy. If bit 0 is at a "1" the device is ready for any valid operation. The status read is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
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(c) 2000 Silicon Storage Technology, Inc. The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. These specifications are subject to change without notice. 514-1 10/00 S71178 1
512 Kbit / 1 Mbit / 2 Mbit Serial Flash SST45VF512 / SST45VF010 / SST45VF020
Advance Information Reset Reset will terminate any operation, e.g., Read, Erase and Program, in progress. It is activated by a high to low transition on the RESET# pin. The device will remain in reset condition as long as RESET# is low. Minimum reset time is 10s. See Figure 14 for reset timing diagram. RESET# is internally pulled-up and could remain unconnected during normal operation. After reset, the device is in standby mode, a high to low transition on CE# is required to start the next operation. An internal power-on reset circuit protects against accidental data writes. Applying a logic level low to RESET# during the power-on process then changing to a logic level high when VDD has reached the correct voltage level will provide additional protection against accidental writes during power on. Read SST ID/Read Device ID The Read SST ID and Read Device ID operations read the JEDEC assigned manufacturer identification and the manufacturer assigned device identification codes. These codes may be used to determine the actual device resident in the system. FUNCTIONAL BLOCK DIAGRAM TABLE 1: PRODUCT IDENTIFICATION Manufacturer's ID Device ID SST45VF512 SST45VF010 SST45VF020 Byte 0000 H 0001 H 0001 H 0001 H Data BF H 41 H 45 H 43 H
514 PGM T1.4
Write Protect The WP# pin provides inadvertent write protection. The WP# pin must be held high for any Erase or Program operation. The WP# pin is "don't care" for all other operations. In typical use, the WP# pin is connected to VSS with a standard pull-down resistor. WP# is then driven high whenever an Erase or Program operation is required. If the WP# pin is tied to VDD with a pull-up resistor, then all operations may occur and the write protection feature is disabled. The WP# pin has an internal pull-up and could remain unconnected when not used.
Address Buffers and Latches
X - Decoder
SuperFlash Cell Array
Y - Decoder
Control Logic
I/O Buffers and Data Latches
Serial Interface
CE#
(c) 2000 Silicon Storage Technology, Inc.
SCK
SI
SO
2
WP# RESET#
514ILL B1.0
S71178
514-1 10/00
512 Kbit / 1 Mbit / 2 Mbit Serial Flash SST45VF512 / SST45VF010 / SST45VF020
Advance Information
WP# VDD CE# SCK
1
8
RESET# VSS SO SI
1 2 3
2 Standard Pinout 7 3 4
Top View Die Up
6 5
514 ILL F01.0
FIGURE 1: PIN ASSIGNMENTS FOR 8-PIN SOIC
4
TABLE 2: PIN DESCRIPTION Symbol Pin Name SCK Serial Clock
5
Functions To provide the timing of the serial interface. Commands, addresses, or input data are latched on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. To transfer commands, addresses, or data serially into the device. Inputs are latched on the rising edge of the serial clock. To transfer data serially out of the device. Data is shifted out on the falling edge of the serial clock. The device is enabled by a high to low transition on CE#. To protect the device from unintentional Write (Erase or Program) operations. When WP# is low, all Erase and Program commands are ignored. When WP# is high, the device may be erased or programmed. This pin has an internal pull-up and could remain unconnected when not used. A high to low transition on RESET# will terminate any operation in progress and reset the internal logic to the standby mode. The device will remain in the reset condition as long as the RESET# is low. Operations may only occur when RESET# is high. This pin has an internal pull-up and could remain unconnected when not used. To provide power supply (2.7-3.6V).
514 PGM T2.2
6 7 8 9 10 11 12 13 14 15 16
SI SO CE# WP#
Serial Data Input Serial Data Output Chip Enable Write Protect
RESET#
Reset
VDD VSS
Power Supply Ground
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit Serial Flash SST45VF512 / SST45VF010 / SST45VF020
Advance Information TABLE 3: DEVICE OPERATION INSTRUCTIONS Bus Cycle Operation/Type Read Sector-Erase2 Chip-Erase Byte-Program Software-Status Read SST ID Read Device ID3 1 Command FFH 20H 60H 10H 9FH 90H 90H 2 Address1 A23-A16 A23-A16 X A23-A16 Dout X X 3 Address A15-A8 A15-A8 X A15-A8 X X 4 Address A7-A0 X X A7-A0 A0=0 A0=1 5 Data X D0H D0H Din BFH Device ID
514 PGM T3.3
6 Dummy X X X X
7 and after Data Dout
Notes: 1. A23-A16 are "Don't Care" for SST45VF512, A23-A17 are "Don't Care" for SST45VF010, A23-A18 are "Don't Care" for SST45VF020. 2. A16-A12 are used to determine sector address, A11-A8 are don't care. 3. With A15-A1 = 0, SST45VF512 Device ID = 41H, is read with A0 = 1. With A16-A1 = 0, SST45VF010 Device ID = 45H, is read with A0 = 1. With A17-A1 = 0, SST45VF020 Device ID = 43H, is read with A0 = 1.
TABLE 4: DEVICE OPERATION TABLE Operation Read Sector-Erase Chip-Erase Byte-Program Software-Status Reset2 Read SST ID Read Device ID SI X X X Din X X X X SO Dout X X X Dout X Dout Dout CE#1 Low Low Low Low Low X Low Low WP# X High High High X X X X RESET# High High High High High Low High High
514 PGM T4.1
Notes: 1. A high to low transition on CE# will be required to start any device operation except for Reset. 2. The RESET# low will return the device to standby and terminate any Erase or Program operation in progress.
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit Serial Flash SST45VF512 / SST45VF010 / SST45VF020
Advance Information Absolute Maximum Stress Ratings (Applied conditions greater than those listed under "Absolute maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this data sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Temperature Under Bias ................................................................................................................. -55C to +125C Storage Temperature ...................................................................................................................... -65C to +150C D. C. Voltage on Any Pin to Ground Potential ............................................................................ -0.5V to VDD + 0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential ........................................................ -1.0V to VDD + 1.0V Package Power Dissipation Capability (Ta = 25C) ........................................................................................... 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) ............................................................................... 240C Output Short Circuit Current1 ................................................................................................................................................................... 50 mA
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OPERATING RANGE Range Ambient Temp Commercial 0 C to +70 C
AC CONDITIONS OF TEST VDD 2.7-3.6V Input Rise/Fall Time ......... 5 ns Output Load ..................... CL = 30 pF See Figures 2 and 3
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TABLE 5: DC OPERATING CHARACTERISTICS VDD = 2.7-3.6V Limits Symbol Parameter Min Max Units IDD ISB ILI ILO IIL VIL VIH VIHC VOL VOH Power Supply Current Read Program and Erase Standby Current Input Leakage Current Output Leakage Current Input Low Current(2) Input Low Voltage Input High Voltage 0.7 VDD Input High Voltage (CMOS) VDD-0.3 Output Low Voltage Output High Voltage VDD-0.2 20 30 15 1 1 360 0.8 mA mA A A A A V V V V V
Test Conditions f = 10 MHz CE# = VIL, VDD = VDD Max. CE# = VIL, VDD = VDD Max. CE# = VIHC, VDD = VDD Max. VIN =GND to VDD, VDD = VDD Max. VOUT =GND to VDD, VDD = VDD Max. WP#, RESET# = GND VDD = VDD Min. VDD = VDD Max. VDD = VDD Max. IOL = 100 A, VDD = VDD Min. IOH = -100 A, VDD = VDD Min.
514 PGM T5.2
9 10 11 12 13 14 15 16
0.2
Note: 1. Outputs shorted for no more than one second. No more than one output shorted at a time. 2. This parameter only applies to WP# and RESET# pins.
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit Serial Flash SST45VF512 / SST45VF010 / SST45VF020
Advance Information TABLE 6: CAPACITANCE (Ta = 25 C, f=1 Mhz, other pins open) Parameter Description Test Condition COUT CIN1
1
Maximum 12 pF 6 pF
514 PGM T6.0
Output Pin Capacitance Input Capacitance
VOUT = 0V VIN = 0v
TABLE 7: RELIABILITY CHARACTERISTICS Symbol Parameter NEND TDR1 VZAP_HBM1 VZAP_MM1 ILTH1
1
Minimum Specification 10,000 100 2000 200 100 + IDD
Units Cycles Years Volts Volts mA
Test Method JEDEC Standard A117 JEDEC Standard A103 JEDEC Standard A114 JEDEC Standard A115 JEDEC Standard 78
514 PGM T7.0
Endurance Data Retention ESD Susceptibility Human Body Model ESD Susceptibility Machine Model Latch Up
Note: 1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 8: AC OPERATING CHARACTERISTICS VDD = 2.7-3.6V Symbol FCLK TSCKH TSCKL TCES TCEH TCPH TCHZ TCLZ TRLZ TDS TDH TOH TV TWPS TWPH TSE TSCE TBP TRST TREC TPURST Parameter Serial Clock Frequency Serial Clock High Time Serial Clock Low Time CE# Setup Time CE# Hold Time CE# High Time CE# High to High-Z Output CE# Low to Low-Z Output RESET# Low to High-Z Output Data In Setup Time Data In Hold Time Output Hold from SCK Change Output Valid from SCK Write Protect Setup Time Write Protect Hold Time Sector-Erase Chip-Erase Byte-Program Reset Pulse Width Reset Recovery Time Reset Time After Power-Up Min 45 45 250 250 250 25 0 25 20 20 0 35 10 10 25 100 20 10 1 10 Limits Max 10 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms s s s s
514 PGM T8.2
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit Serial Flash SST45VF512 / SST45VF010 / SST45VF020
Advance Information
1
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
2
514 ILL F02.0
VILT
3 4 5 6 7 8
AC test inputs are driven at VIHT (0.9 VDD) for a logic "1" and VILT (0.1 VDD) for a logic "0". Measurement reference points for inputs and outputs are at VIT (0.5 VDD) and VOT (0.5 VDD) Input rise and fall times (10% are <5 ns.
y90%)
Note: VIT-VINPUT Test VOT-VOUTPUT Test VIHT-VINPUT HIGH Test VILT-VINPUT LOW Test
FIGURE 2: AC INPUT/OUTPUT REFERENCE WAVEFORMS
TO TESTER
9
TO DUT CL
514 ILL F03.0
10 11
FIGURE 3: A TEST LOAD EXAMPLE
12 13 14 15 16
(c) 2000 Silicon Storage Technology, Inc.
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512 Kbit / 1 Mbit / 2 Mbit Serial Flash SST45VF512 / SST45VF010 / SST45VF020
Advance Information
WP# TCPH CE# TCES SCK TDS SI TDH TSCKH TSCKL TCEH
DATA VALID HIGH-Z HIGH-Z
514 ILL F04.0
SO
FIGURE 4: SERIAL INPUT TIMING DIAGRAM (INACTIVE SERIAL CLOCK LOW - MODE 0)
WP#
CE# TSCKH TSCKL SCK TCLZ SO TV SI
514 ILL F05.0
TCEH
TOH DATA VALID
TCHZ
FIGURE 5: SERIAL OUTPUT TIMING DIAGRAM (INACTIVE SERIAL CLOCK LOW - MODE 0)
(c) 2000 Silicon Storage Technology, Inc.
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S71178
514-1 10/00
512 Kbit / 1 Mbit / 2 Mbit Serial Flash SST45VF512 / SST45VF010 / SST45VF020
Advance Information
1
WP# TCPH CE# TCES SCK TDS SI TDH TSCKL TSCKH TCEH
2 3 4
DATA VALID HIGH-Z HIGH-Z
514 ILL F17.0
5 6 7 8 9
SO
FIGURE 6: SERIAL INPUT TIMING DIAGRAM (INACTIVE SERIAL CLOCK HIGH - MODE 3)
WP#
10
CE# TSCKH TSCKL SCK TCLZ SO TV SI
514 ILL F18.0
TCEH
11
TCHZ
TOH DATA VALID
12 13 14 15
FIGURE 7: SERIAL OUTPUT TIMING DIAGRAM (INACTIVE SERIAL CLOCK HIGH - MODE 3)
16
(c) 2000 Silicon Storage Technology, Inc.
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S71178
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512 Kbit / 1 Mbit / 2 Mbit Serial Flash SST45VF512 / SST45VF010 / SST45VF020
Advance Information
TWPS WP#
TWPH
CE# TSE 012345 SCK 678 15 16 23 24 31 32 39 40 47
SELF-TIMED SECTORERASE CYCLE
SI
00100000
ADD.
ADD.
X
D0H
X
SO
HIGH IMPEDANCE
514 ILL F06.1
FIGURE 8: SECTOR-ERASE TIMING DIAGRAM
TWPS WP#
TWPH
CE# TSCE 012345 SCK 678 15 16 23 24 31 32 39 40 47
SELF-TIMED CHIPERASE CYCLE
SI
01100000
X
X
X
D0H
X
SO
HIGH IMPEDANCE
514 ILL F07.1
FIGURE 9: CHIP-ERASE TIMING DIAGRAM
(c) 2000 Silicon Storage Technology, Inc.
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S71178
514-1 10/00
512 Kbit / 1 Mbit / 2 Mbit Serial Flash SST45VF512 / SST45VF010 / SST45VF020
Advance Information
1
TWPS WP# TWPH
2 3
012345 678 15 16 23 24 31 32 39 40 47 TBP
SELF-TIMED BYTEPROGRAM CYCLE
CE#
SCK
4 5 6
SI
00010000
ADD.
ADD.
ADD. MSB
Din LSB
X
SO
HIGH IMPEDANCE
514 ILL F08.1
FIGURE 10: BYTE-PROGRAM TIMING DIAGRAM
7 8 9 10
WP#
11
CE# 012345 SCK 678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71
12 13
SI
11111111
ADD.
ADD.
ADD.
X
X N Dout MSB N+1 Dout MSB N+2 Dout MSB
514 ILL F10.1
SO
HIGH IMPEDANCE
14 15 16
FIGURE 11: READ TIMING DIAGRAM
(c) 2000 Silicon Storage Technology, Inc.
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S71178
514-1 10/00
512 Kbit / 1 Mbit / 2 Mbit Serial Flash SST45VF512 / SST45VF010 / SST45VF020
Advance Information
WP#
CE# 012345 SCK 678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71
SI
10010000
X
X
ADD1
SO
HIGH IMPEDANCE
Dout1 MSB LSB
514 ILL F19.5
Note: 1. SST Manufacturer's ID = BFH is read with A0=0 SST45VF512 Device ID = 41H is read with A0=1 SST45VF010 Device ID = 45H is read with A0=1 SST45VF020 Device ID = 43H is read with A0=1
FIGURE 12: READ-ID TIMING DIAGRAM
WP#
CE# 012345 SCK 678 9 10 11 12 13 14 15 16 23 24 31
SI
10011111 HIGH IMPEDANCE MSB
SO
DATA
DATA MSB
DATA MSB
514 ILL F11.1
FIGURE 13: SOFTWARE-STATUS TIMING DIAGRAM
(c) 2000 Silicon Storage Technology, Inc.
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S71178
514-1 10/00
512 Kbit / 1 Mbit / 2 Mbit Serial Flash SST45VF512 / SST45VF010 / SST45VF020
Advance Information
CE# TREC SCK TCES
1
...
TRST
2 3
RESET#
HIGH IMPEDANCE SO
... ...
TRLZ
HIGH IMPEDANCE
4 5
SI
514 ILL F20.0
6 7 8
FIGURE 14: RESET TIMING DIAGRAM (INACTIVE CLOCK POLARITY LOW SHOWN)
VDD TPURST
9
TREC
RESET#
10
514 ILL F13.0
CE#
11 12
FIGURE 15: POWER-ON RESET TIMING DIAGRAM
TWPS WP#
TWPH
13 14 15
514 ILL F14.0
TCPH CE# TCES SCK TCEH
16
FIGURE 16: WRITE PROTECT TIMING DIAGRAM
(c) 2000 Silicon Storage Technology, Inc. S71178 514-1 10/00
13
512 Kbit / 1 Mbit / 2 Mbit Serial Flash SST45VF512 / SST45VF010 / SST45VF020
Advance Information
Device SST45VFxxx
-
Speed Suffix1 XXX - XX -
Suffix2 XX Package Modifier A = 8 pins Package Type S = SOIC Temperature Range C = Commercial = 0 to 70C Minimum Endurance 4 = 10,000 cycles Operating Frequency 10 = 10 MHz Device Density 512 = 512 Kilobit 010 = 1 Megabit 020 = 2 Megabit Voltage Range V = 2.7-3.6V
SST45VF512 Valid combinations SST45VF512-10-4C-SA SST45VF010 Valid combinations SST45VF010-10-4C-SA SST45VF020 Valid combinations SST45VF020-10-4C-SA
Example: Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations.
(c) 2000 Silicon Storage Technology, Inc.
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S71178
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512 Kbit / 1 Mbit / 2 Mbit Serial Flash SST45VF512 / SST45VF010 / SST45VF020
Advance Information PACKAGING DIAGRAMS
1
4.00 3.80 6.20 5.80
2 3
Pin #1 Identifier
4
5.0 4.8
5
45 1.75 1.35 7 4 places .51 .33
Note:
7 4 places 0 8
6 7 8 9
1.27 BSC
0.25 0.10
0.25 0.19
1.27 0.40
8.soic-SA-ILL.3
1. Complies with JEDEC publication 95 MS-012 AA dimensions, although some dimensions may be more stringent. 2. All linear dimensions are in millimeters (min/max). 3. Coplanarity: 0.1 (.05) mm.
8-PIN SMALL OUTLINE INTEGRATED CIRCUIT PACKAGE (SOIC) SST PACKAGE CODE: SA
10 11 12 13 14 15 16
(c) 2000 Silicon Storage Technology, Inc.
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S71178
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512 Kbit / 1 Mbit / 2 Mbit Serial Flash SST45VF512 / SST45VF010 / SST45VF020
Advance Information
Silicon Storage Technology, Inc. * 1171 Sonora Court * Sunnyvale, CA 94086 * Telephone 408-735-9110 * Fax 408-735-9036 www.SuperFlash.com or www.ssti.com * Literature FaxBack 888-221-1178, International 732-544-2873
(c) 2000 Silicon Storage Technology, Inc.
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